R XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000E Electrical Specifications Definition of Terms In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device families. Values are subject to change. Use as estimates, not for production. Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final. Except for pin-to-pin input and output parameters, the a.c. parameter delay specifications included in this document are derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction temperature conditions. All specifications subject to change without notice. XC4000E DC Characteristics Absolute Maximum Ratings Symbol VCC VIN VTS TSTG TSOL TJ Description Supply voltage relative to GND Input voltage relative to GND (Note 1) Voltage applied to 3-state output (Note 1) Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) Ceramic packages Junction Temperature Plastic packages Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 +150 +125 Units V V V C C C C Note 1: Maximum DC excursion above Vcc or below Ground must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to VCC + 2.0 V, provided this over or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Recommended Operating Conditions Symbol VCC Description Supply voltage relative to GND, TJ = -0 C to +85C Supply voltage relative to GND, TJ = -40C to +100C Supply voltage relative to GND, TC = -55C to +125C VIH High-Level Input Voltage VIL Low-Level Input Voltage TIN Notes: Commercial Industrial Military TTL inputs CMOS inputs TTL inputs CMOS inputs Min 4.75 4.5 4.5 2.0 70% 0 0 Input signal transition time Max 5.25 5.5 5.5 VCC 100% 0.8 20% 250 Units V V V V VCC V VCC ns At junction temperatures above those listed above, all delay parameters increase by 0.35% per C. Input and output measurement thresholds for TTL are 1.5 V and for CMOS are 2.5 V. February 11, 2000 (Version 1.8) 6-101 6 R XC4000E and XC4000X Series Field Programmable Gate Arrays DC Characteristics Over Operating Conditions Symbol VOH VOL Description High-level output voltage @ IOH = -4.0mA, VCC min High-level output voltage @ IOH = -1.0mA, VCC min Low-level output voltage @ IOL = 12.0mA, VCC min (Note 1) ICCO Quiescent FPGA supply current (Note 2) IL CIN Input or output leakage current Input capacitance (sample tested) IRIN* IRLL* Pad pull-up (when selected) @ VIN = 0V (sample tested) Horizontal Longline pull-up (when selected) @ logic Low TTL outputs CMOS outputs TTL outputs CMOS outputs Commercial Industrial Military Min 2.4 VCC-0.5 -10 PQFP and MQFP packages Other packages -0.02 0.2 Max 0.4 0.4 3.0 6.0 6.0 +10 10 Units V V V V mA mA mA A pF 16 -0.25 2.5 pF mA mA Notes: With 50% of the outputs simultaneously sinking 12mA, up to a maximum of 64 pins. With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND, and the FPGA configured with a Development system Tie option. *Characterized Only. 6-102 February 11, 2000 (Version 1.8) R XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000E Switching Characteristics Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Global Buffer Switching Characteristic Guidelines Description From pad through Primary buffer, to any clock K From pad through Secondary buffer, to any clock K Speed Grade Symbol Device XC4003E TPG XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E TSG XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E February 11, 2000 (Version 1.8) -4 Max 7.0 7.0 7.5 8.0 11.0 11.5 12.0 12.5 7.5 7.5 8.0 8.5 11.5 12.0 12.5 13.0 -3 Max 4.7 4.7 5.3 6.1 6.3 6.8 7.0 7.2 5.2 5.2 5.8 6.6 6.8 7.3 7.5 7.7 -2 Max 4.0 4.3 5.2 5.2 5.4 5.8 6.4 6.9 4.4 4.7 5.6 5.6 5.8 6.2 6.7 7.2 -1 Max 3.5 3.8 4.6 4.6 4.8 5.2 6.0 - 4.0 4.3 5.1 5.1 5.3 5.7 6.5 - Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 6-103 6 R XC4000E and XC4000X Series Field Programmable Gate Arrays Horizontal Longline Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless otherwise noted. The following guidelines reflect worst-case values over the recommended operating conditions. Description Speed Grade Symbol Device -4 Max -3 Max -2 Max -1 Max Units XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E All devices 5.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 5.0 6.0 7.8 8.1 10.5 11.0 12.0 12.0 5.5 7.0 7.5 8.0 8.5 8.7 11.0 11.0 1.8 4.2 5.0 5.9 6.3 6.4 7.2 8.2 9.1 4.2 5.3 6.4 6.8 6.9 7.7 8.7 9.6 4.6 6.0 6.7 7.1 7.3 7.5 8.4 8.4 1.5 3.4 4.0 4.7 5.0 5.1 5.7 7.3 7.3 3.6 4.5 5.4 5.8 5.9 6.5 8.7 9.6 3.9 5.7 5.7 6.0 6.2 7.0 7.1 7.1 1.3 2.9 3.4 4.0 4.3 4.4 4.9 5.6 - 3.1 3.8 4.6 4.9 5.0 5.5 7.4 - 3.5 4.7 4.9 5.2 5.4 6.2 6.3 - 1.1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E 20.0 23.0 25.0 27.0 29.0 32.0 35.0 42.0 9.0 10.0 11.5 12.5 13.5 15.0 16.0 18.0 14.0 16.0 18.0 20.0 22.0 26.0 32.5 39.1 7.0 8.0 9.0 10.0 11.0 13.0 14.8 16.5 14.0 16.0 18.0 20.0 22.0 26.0 32.5 39.1 6.0 6.8 7.7 8.5 9.4 11.7 14.8 16.5 12.0 14.0 16.0 16.0 18.0 21.0 26.0 - 5.4 5.8 6.5 7.5 8.0 9.4 10.5 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TBUF driving a Horizontal Longline (LL): I going High or Low to LL going High or Low, while T is Low. Buffer is constantly active. (Note1) TIO1 I going Low to LL going from resistive pull-up High to active Low. TBUF configured as open-drain. TIO2 (Note1) T going Low to LL going from resistive pull-up or floating High to active Low. TBUF configured as open-drain or active buffer with I = Low. TON (Note1) T going High to TBUF going inactive, not driving LL T going High to LL going from Low to High, pulled up by a single resistor. TOFF TPUS (Note 1) T going High to LL going from Low to High, pulled up by two resistors. (Note1) TPUF Note 1: These values include a minimum load. Use the static timing analyzer to determine the delay for each destination. 6-104 February 11, 2000 (Version 1.8) R XC4000E and XC4000X Series Field Programmable Gate Arrays Wide Decoder Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless otherwise noted. The following guidelines reflect worst-case values over the recommended operating conditions. Description Full length, both pull-ups, inputs from IOB I-pins Symbol TWAF Full length, both pull-ups, inputs from internal logic TWAFL Half length, one pull-up, inputs from IOB I-pins TWAO Half length, one pull-up, inputs from internal logic TWAOL Speed Grade Device XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E -4 Max 9.2 9.5 12.0 12.5 15.0 16.0 17.0 18.0 12.0 12.5 14.0 16.0 18.0 19.0 20.0 21.0 10.5 10.5 13.5 14.0 16.0 17.0 18.0 19.0 12.0 12.5 14.0 16.0 18.0 19.0 20.0 21.0 -3 Max 5.0 6.0 7.0 8.0 9.0 11.0 13.9 16.9 7.0 8.0 9.0 10.0 11.0 13.0 15.5 18.9 6.0 7.0 8.0 9.0 10.0 12.0 15.0 17.6 8.0 9.0 10.0 11.0 12.0 14.0 16.8 19.6 -2 Max 5.0 6.0 7.0 8.0 9.0 11.0 13.9 16.9 7.0 8.0 9.0 10.0 11.0 13.0 15.5 18.9 6.0 7.0 8.0 9.0 10.0 12.0 15.0 17.6 8.0 9.0 10.0 11.0 12.0 14.0 16.8 19.6 -1 Max 4.3 5.1 6.0 6.5 7.5 8.6 10.1 - 5.5 6.4 7.0 7.5 8.5 10.0 11.8 - 5.1 6.0 6.5 7.0 7.5 10.0 11.8 - 6.0 7.0 7.6 8.4 9.2 10.8 12.6 - Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1: These delays are specified from the decoder input to the decoder output. Note 2: Fewer than the specified number of pullup resistors can be used, if desired. Using fewer pullups reduces power consumption but increases delays. Use the static timing analyzer to determine delays if fewer pullups are used. February 11, 2000 (Version 1.8) 6-105 6 R XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000E CLB Characteristics Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless otherwise noted CLB Switching Characteristics Guidelines Speed Grade Description Combinatorial Delays F/G inputs to X/Y outputs F/G inputs via H to X/Y outputs C inputs via SR through H to X/Y outputs C inputs via H to X/Y outputs C inputs via DIN through H to X/Y outputs CLB Fast Carry Logic Operand inputs (F1, F2, G1, G4) to COUT Add/Subtract input (F3) to COUT Initialization inputs (F1, F3) to COUT CIN through function generators to X/Y outputs CIN to COUT, bypass function generators Sequential Delays Clock K to outputs Q Setup Time before Clock K F/G inputs F/G inputs via H C inputs via H0 through H C inputs via H1 through H C inputs via H2 through H C inputs via DIN C inputs via EC C inputs via S/R, going Low (inactive) CIN input via F/G CIN input via F/G and H 6-106 -4 Symbol Min -3 Max Min -2 Max Min -1 Max Min Max Units TILO TIHO THH0O THH1O THH2O 2.7 4.7 4.1 3.7 4.5 2.0 4.3 3.3 3.6 3.6 1.6 2.7 2.4 2.2 2.6 1.3 2.2 1.9 1.6 1.9 ns ns ns ns ns TOPCY TASCY TINCY TSUM 3.2 5.5 1.7 3.8 2.6 4.4 1.7 3.3 2.1 3.7 1.4 2.6 1.7 2.5 1.2 1.8 ns ns ns ns TBYP 1.0 0.7 0.6 0.5 ns TCKO 3.7 2.8 2.8 1.9 ns TICK TIHCK THH0CK THH1CK THH2CK TDICK TECCK TRCK TCCK TCHCK 4.0 6.1 4.5 5.0 4.8 3.0 4.0 4.2 2.5 4.2 3.0 4.6 3.6 4.1 3.8 2.4 3.0 4.0 2.1 3.5 2.4 3.9 3.5 3.3 3.7 2.0 2.6 4.0 1.8 2.8 2.4 2.1 2.5 1.0 2.0 1.5 ns ns ns ns ns ns ns ns ns ns February 11, 2000 (Version 1.8) R XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000E CLB Characteristics Guidelines (Continued) Speed Grade Description Symbol Hold Time after Clock K F/G inputs TCKI F/G inputs via H TCKIH C inputs via H0 through H TCKHH0 TCKHH1 C inputs via H1 through H TCKHH2 C inputs via H2 through H C inputs via DIN TCKDI C inputs via EC TCKEC C inputs via SR, going Low (inactive) TCKR Clock Clock High time TCH Clock Low time TCL Set/Reset Direct Width (High) TRPW Delay from C inputs via S/R, TRIO going High to Q Master Set/Reset (Note 1) Width (High or Low) TMRW Delay from Global Set/Reset net to Q TMRQ Global Set/Reset inactive to first TMRK active clock K edge Toggle Frequency (Note 2) FTOG -4 Min -3 Max Min -2 Max Min -1 Max Min Max Units 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ns ns ns ns ns ns ns ns 4.5 4.5 4.0 4.0 4.0 4.0 3.0 3.0 ns ns 5.5 4.0 6.5 13.0 4.0 4.0 11.5 3.0 4.0 11.5 3.0 ns ns 23.0 18.7 17.4 10.0 15.0 ns ns 111 125 125 166 MHz Note 1: Timing is based on the XC4005E. For other devices see the static timing analyzer. Note 2: Export Control Max. flip-flop toggle rate. February 11, 2000 (Version 1.8) 6-107 6 R XC4000E and XC4000X Series Field Programmable Gate Arrays CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless otherwise noted. Single Port RAM Speed Grade -4 -3 -2 -1 Units Size Symbol Min Max Min Address write cycle time (clock K period) 16x2 32x1 TWCS TWCTS 15.0 15.0 Clock K pulse width (active edge) 16x2 32x1 TWPS TWPTS 7.5 7.5 Address setup time before clock K 16x2 32x1 TASS TASTS 2.8 2.8 2.4 2.4 Address hold time after clock K 16x2 32x1 TAHS TAHTS 0 0 DIN setup time before clock K 16x2 32x1 TDSS TDSTS DIN hold time after clock K 16x2 32x1 WE setup time before clock K Max Min Max Min Max Write Operation 14.4 14.4 8.0 8.0 ns ns 4.0 4.0 ns ns 2.0 2.0 1.5 1.5 ns ns 0 0 0 0 0 0 ns ns 3.5 2.5 3.2 1.9 2.7 1.7 1.5 1.5 ns ns TDHS TDHTS 0 0 0 0 0 0 0 0 ns ns 16x2 32x1 TWSS TWSTS 2.2 2.2 2.0 2.0 1.6 1.6 1.5 1.5 ns ns WE hold time after clock K 16x2 32x1 TWHS TWHTS 0 0 0 0 0 0 0 0 ns ns Data valid after clock K 16x2 32x1 TWOS TWOTS 1 ms 1 ms 11.6 11.6 7.2 7.2 1 ms 1 ms 10.3 11.6 5.8 5.8 8.8 10.3 1 ms 1 ms 7.9 9.3 6.5 7.0 ns ns Note 1: Timing for the 16x1 RAM option is identical to 16x2 RAM timing. Note 2: Applicable Read timing specifications are identical to Level-Sensitive Read timing. Dual-Port RAM Speed Grade -4 -3 -2 -1 Units Size Symbol Min 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 TWCDS TWPDS TASDS TAHDS TDSDS TDHDS TWSDS TWHDS TWODS 15.0 7.5 2.8 0 2.2 0 2.2 0.3 Max Min Max Min Max Min 11.6 5.8 1 ms 2.1 0 1.6 0 1.6 0 7.0 8.0 4.0 1.5 0 1.5 0 1.5 0 Max Write Operation Address write cycle time (clock K period) Clock K pulse width (active edge) Address setup time before clock K Address hold time after clock K DIN setup time before clock K DIN hold time after clock K WE setup time before clock K WE hold time after clock K Data valid after clock K 1 ms 14.4 7.2 2.5 0 2.5 0 1.8 0 10.0 1 ms 7.8 6.5 ns ns ns ns ns ns ns ns ns Note: Applicable Read timing specifications are identical to Level-Sensitive Read timing 6-108 February 11, 2000 (Version 1.8) R XC4000E and XC4000X Series Field Programmable Gate Arrays CLB RAM Synchronous (Edge-Triggered) Write Timing Waveforms TWPS TWPDS WCLK (K) WCLK (K) TWHS TWSS WE TWSDS TWHDS TDSDS TDHDS TASDS TAHDS WE TDHS TDSS DATA IN DATA IN TASS TAHS ADDRESS ADDRESS TILO DATA OUT TWOS OLD TWODS DATA OUT NEW OLD NEW X6474 X6461 Single Port TILO TILO TILO Dual Port 6 February 11, 2000 (Version 1.8) 6-109 R XC4000E and XC4000X Series Field Programmable Gate Arrays CLB Level-Sensitive RAM Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless otherwise noted. Speed Grade -4 -3 -2 -1 Units Description Size Symbol Min Max Min Max Min Max Min Max Address write cycle time 16x2 32x1 TWC TWCT 8.0 8.0 8.0 8.0 8.0 8.0 8.0 8.0 ns ns Write Enable pulse width (High) 16x2 32x1 TWP TWPT 4.0 4.0 4.0 4.0 4.0 4.0 4.0 4.0 ns ns Address setup time before WE 16x2 32x1 TAS TAST 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 ns ns Address hold time after end of WE 16x2 32x1 TAH TAHT 2.5 2.0 2.0 2.0 2.0 2.0 2.0 2.0 ns ns DIN setup time before end of WE 16x2 32x1 TDS TDST 4.0 5.0 2.2 2.2 0.8 0.8 0.8 0.8 ns ns DIN hold time after end of WE 16x2 32x1 TDH TDHT 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 ns ns Address read cycle time 16x2 32x1 TRC TRCT 4.5 6.5 3.1 5.5 2.6 3.8 2.6 3.8 ns ns Data valid after address change (no Write Enable) 16x2 32x1 TILO TIHO Write Operation Read Operation 2.7 4.7 1.8 3.2 1.6 2.7 1.6 2.7 ns ns Read Operation, Clocking Data into Flip-Flop Address setup time before clock K 16x2 32x1 TICK TIHCK 4.0 6.1 3.0 4.6 2.4 3.9 2.4 3.9 ns ns Data valid after WE goes active (DIN stable before WE) 16x2 32x1 TWO TWOT 10.0 12.0 6.0 7.3 4.9 5.6 4.9 5.6 ns ns Data valid after DIN (DIN changes during WE) 16x2 32x1 TDO TDOT 9.0 11.0 6.6 7.6 5.8 6.2 5.8 6.2 ns ns Read During Write Read During Write, Clocking Data into Flip-Flop WE setup time before clock K 16x2 32x1 TWCK TWCKT 8.0 9.6 6.0 6.8 5.1 5.8 5.1 5.8 ns ns Data setup time before clock K 16x2 32x1 TDCK TDCKT 7.0 8.0 5.2 6.2 4.4 5.3 4.4 5.3 ns ns Note 1: Timing for the 16x1 RAM option is identical to 16x2 RAM timing. 6-110 February 11, 2000 (Version 1.8) R XC4000E and XC4000X Series Field Programmable Gate Arrays CLB Level-Sensitive RAM Timing Waveforms T WC ADDRESS WRITE TAS T WP T AH WRITE ENABLE T DS DATA IN REQUIRED READ WITHOUT WRITE X,Y OUTPUTS T DH T ILO VALID VALID READ, CLOCKING DATA INTO FLIP-FLOP T ICK T CH CLOCK 6 T CKO VALID (OLD) XQ, YQ OUTPUTS VALID (NEW) READ DURING WRITE T WP WRITE ENABLE T DH DATA IN (stable during WE) T WO X, Y OUTPUTS VALID DATA IN (changing during WE) OLD VALID NEW T DO T WO X, Y OUTPUTS VALID (PREVIOUS) VALID (OLD) VALID (NEW) READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP T WP WRITE ENABLE T WCK T DCK DATA IN CLOCK T CKO XQ, YQ OUTPUTS X2640 February 11, 2000 (Version 1.8) 6-111 R XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL I/O) Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values apply to all XC4000E devices unless otherwise noted. Speed Grade Symbol Device XC4003E TICKOF Description Global Clock to Output (fast) using OFF TPG . . . . . OFF Global Clock-to-Output Delay (Max) X3202 Global Clock to Output (slew-limited) using OFF TPG TICKO . . . . . OFF Global Clock-to-Output Delay (Max) X3202 Input Setup Time, using IFF (no delay) D Input Set - Up & Hold Time TPSUF (Min) IFF TPG X3201 Input Hold Time, using IFF (no delay) TPHF D Input Set - Up & Hold Time (Min) IFF TPG X3201 Input Setup Time, using IFF (with delay) D Input Set - Up & Hold Time TPSU (Min) IFF TPG X3201 Input Hold Time, using IFF (with delay) TPH D Input Set - Up & Hold Time (Min) IFF TPG X3201 -4 -3 -2 -1 XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E 12.5 14.0 14.5 15.0 16.0 16.5 17.0 17.0 10.2 10.7 10.7 10.8 10.9 11.0 11.0 12.6 8.7 9.1 9.1 9.2 9.3 9.4 10.2 10.8 5.8 6.2 6.4 6.6 6.8 7.2 7.4 - ns ns ns ns ns ns ns ns XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E 16.5 18.0 18.5 19.0 20.0 20.5 21.0 21.0 14.0 14.7 14.7 14.8 14.9 15.0 15.1 15.3 11.5 12.0 12.0 12.1 12.2 12.8 12.8 13.0 7.8 8.2 8.4 8.6 8.8 9.2 9.4 - ns ns ns ns ns ns ns ns XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E 2.5 2.0 1.9 1.4 1.0 0.5 0 0 2.3 1.2 1.0 0.6 0.2 0 0 0 2.3 1.2 1.0 0.6 0.2 0 0 0 1.5 0.8 0.6 0.2 0 0 0 - ns ns ns ns ns ns ns ns XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E 4.0 4.6 5.0 6.0 6.0 7.0 7.5 8.0 4.0 4.5 4.7 5.1 5.5 6.5 6.7 7.0 4.0 4.5 4.7 5.1 5.5 5.5 5.7 5.9 1.5 2.0 2.0 2.5 2.5 3.0 3.5 - ns ns ns ns ns ns ns ns XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E 8.5 8.5 8.5 8.5 8.5 8.5 9.5 9.5 7.0 7.0 7.0 7.0 7.0 7.0 7.0 7.6 6.0 6.0 6.0 6.0 6.0 6.0 6.8 6.8 5.0 5.0 5.0 5.0 5.0 5.0 5.0 - ns ns ns ns ns ns ns ns XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - ns ns ns ns ns ns ns ns Units OFF = Output Flip-Flop, IFF = Input Flip-Flop or Latch 6-112 February 11, 2000 (Version 1.8) R XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000E IOB Input Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values apply to all XC4000E devices unless otherwise noted. Description Speed Grade Symbol Device -4 Min -3 Max Min -2 Max Min -1 Max Min Max Units Propagation Delays (TTL Inputs) Pad to I1, I2 Pad to I1, I2 via transparent latch, no delay with delay TPID All devices 3.0 2.5 2.0 1.4 ns TPLI TPDLI All devices XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E 4.8 10.4 10.8 10.8 10.8 11.0 11.4 13.8 13.8 3.6 9.3 9.6 10.2 10.6 10.8 11.2 12.4 13.7 3.6 6.9 7.4 8.1 8.2 8.3 9.8 11.5 12.4 2.8 6.4 6.5 6.9 7.0 7.3 8.4 9.0 - ns ns ns ns ns ns ns ns ns TPIDC All devices 5.5 4.1 3.7 1.9 ns TPLIC TPDLIC All devices XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E 8.8 16.5 16.5 16.8 17.3 17.5 18.0 20.8 20.8 6.8 12.4 13.2 13.4 13.8 14.0 14.4 15.6 15.6 6.2 11.0 11.9 12.1 12.4 12.6 13.0 14.0 14.0 3.3 6.9 7.0 7.4 7.4 7.8 9.0 9.5 - ns ns ns ns ns ns ns ns ns TIKRI All devices 5.6 2.8 2.8 2.7 ns TIKLI All devices 6.2 4.0 3.9 3.2 ns Propagation Delays (CMOS Inputs) Pad to I1, I2 Pad to I1, I2 via transparent latch, no delay with delay Propagation Delays Clock (IK) to I1, I2 (flip-flop) Clock (IK) to I1, I2 (latch enable, active Low) Hold Times (Note 1) Pad to Clock (IK), no delay with delay Clock Enable (EC) to Clock (IK), no delay with delay TIKPI TIKPID All devices All devices TIKEC All devices TIKECD All devices 0 0 0 0 0 0 0 0 ns ns 1.5 0 1.5 0 0.9 0 0 0 ns ns Note 1: Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table. Note 2: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source. February 11, 2000 (Version 1.8) 6-113 6 R XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000E IOB Input Switching Characteristic Guidelines (Continued) Speed Grade Description Symbol Device Setup Times (TTL Inputs) Pad to Clock (IK), no delay TPICK All devices with delay TPICKD XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E Setup Time (CMOS Inputs) Pad to Clock (IK), no delay TPICKC All devices with delay TPICKDC XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E (TTL or CMOS) Clock Enable (EC) to Clock (IK), no delay TECIK All devices with delay TECIKD XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E Global Set/Reset (Note 3) Delay from GSR net TRRI through Q to I1, I2 GSR width TMRW GSR inactive to first active TMRI Clock (IK) edge Note 1: Note 2: Note 3: 6-114 -4 Min -3 Max Min -2 Max Min -1 Max Min Max Units 4.0 10.9 10.9 10.9 11.1 11.3 11.8 14.0 14.0 2.6 8.2 8.7 9.2 9.6 9.8 10.2 11.4 11.4 2.0 6.0 6.1 6.2 6.3 6.4 7.9 9.4 10.0 1.5 4.8 5.1 5.8 5.8 6.0 7.6 8.2 - ns ns ns ns ns ns ns ns ns 6.0 12.0 12.0 12.3 12.8 13.0 13.5 16.0 16.0 3.3 8.8 9.7 9.9 10.3 10.5 10.9 12.1 12.1 2.4 6.9 8.0 8.1 8.2 8.3 10.0 12.1 12.1 2.4 5.3 5.6 6.3 6.3 6.5 7.9 8.1 - ns ns ns ns ns ns ns ns ns 3.5 10.4 10.4 10.4 10.4 10.7 11.1 14.0 14.0 2.5 8.1 8.5 9.1 9.5 9.7 10.1 11.3 11.3 2.1 4.3 5.6 6.7 6.9 7.1 9.0 10.6 11.0 1.5 4.3 5.0 6.0 6.0 6.5 8.0 9.0 - ns ns ns ns ns ns ns ns ns 12.0 13.0 7.8 11.5 6.8 11.5 6.8 10.0 ns ns Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source. Timing is based on the XC4005E. For other devices see the XACT timing calculator. February 11, 2000 (Version 1.8) R XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000E IOB Output Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless otherwise noted. Speed Grade Description Symbol Propagation Delays (TTL Output Levels) Clock (OK) to Pad, fast TOKPOF slew-rate limited TOKPOS Output (O) to Pad, fast TOPF slew-rate limited TOPS 3-state to Pad hi-Z TTSHZ (slew-rate independent) 3-state to Pad active and valid, fast TTSONF slew-rate limited TTSONS Propagation Delays (CMOS Output Levels) Clock (OK) to Pad, fast TOKPOFC slew-rate limited TOKPOSC Output (O) to Pad, fast TOPFC slew-rate limited TOPSC 3-state to Pad hi-Z TTSHZC (slew-rate independent) 3-state to Pad active and valid, fast TTSONFC slew-rate limited TTSONSC Note 1: Note 2: -4 Min -3 Max Min -2 Max Min -1 Max Min Max Units 7.5 11.5 8.0 12.0 5.0 6.5 9.5 5.5 8.5 4.2 4.5 7.0 4.8 7.3 3.8 3.0 5.0 3.2 5.2 3.0 ns ns ns ns ns 9.7 13.7 8.1 11.1 7.3 9.8 6.8 8.8 ns ns 9.5 13.5 10.0 14.0 5.2 7.8 11.6 9.7 13.4 4.3 7.0 10.4 8.7 12.1 3.9 4.0 7.0 4.0 6.0 3.9 ns ns ns ns ns 9.1 13.1 7.6 11.4 6.8 10.2 6.8 8.8 ns ns Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the "Additional XC4000 Data" section of the Programmable Logic Data Book. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source. February 11, 2000 (Version 1.8) 6-115 6 R XC4000E and XC4000X Series Field Programmable Gate Arrays IOB Output Switching Characteristics Guidelines (Continued) Speed Grade Description Symbol Setup and Hold Output (O) to clock (OK) TOOK setup time Output (O) to clock (OK) TOKO hold time TECOK Clock Enable (EC) to clock (OK) setup Clock Enable (EC) to TOKEC clock (OK) hold Clock Clock High TCH Clock Low TCL Global Set/Reset (Note 3) Delay from GSR net to Pad TRPO GSR width TMRW GSR inactive to first active TMRO clock (OK) edge Note 1: Note 2: Note 3: 6-116 -4 Min -3 Max Min -2 Max Min -1 Max Min Max Units 5.0 4.6 3.8 2.3 ns 0 0 0 0 ns 4.8 3.5 2.7 2.0 ns 1.2 1.2 0.5 0 ns 4.5 4.5 4.0 4.0 4.0 4.0 15.0 13.0 11.8 11.5 8.7 11.5 3.0 3.0 ns ns 7.0 ns ns Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the "Additional XC4000 Data" section of the Programmable Logic Data Book. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source. Timing is based on the XC4005E. For other devices see the XACT timing calculator. February 11, 2000 (Version 1.8) R XC4000E and XC4000X Series Field Programmable Gate Arrays XC4000E Boundary Scan (JTAG) Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC4000E devices unless otherwise noted. Speed Grade Description Symbol Setup Times Input (TDI) to clock (TCK) TTDITCK Input (TMS) to clock (TCK) TTMSTCK Hold Times Input (TDI) to clock (TCK) TTCKTDI Input (TMS) to clock (TCK) TTCKTMS Propagation Delay Clock (TCK) to Pad (TDO) TTCKPO Clock Clock (TCK) High TTCKH Clock (TCK) Low TTCKL Frequency FMAX Note 1: Note 2: Note 3: -4 Min -3 Max Min -2 Max Min -1 Max Min Max Units 30.0 15.0 30.0 15.0 30.0 15.0 20.0 10.0 ns ns 0 0 0 0 0 0 0 0 ns ns 30.0 30.0 5.0 5.0 5.0 5.0 15.0 30.0 5.0 5.0 15.0 20.0 ns 25.0 ns ns MHz 4.0 4.0 15.0 Input setup and hold times and clock-to-pad times are specified with respect to external signal pins. Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the "Additional XC4000 Data" section of the Programmable Logic Data Book. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source. Revision Control Version Nature of Changes 3/30/98 (1.5) As submitted for the 1999 data book 1/29/99 (1.5) Updated Switching Characteristics Tables 5/14/99 (1.6) Replaced Electrical Specification and pinout pages for E, EX, and XL families with separate updates and added URL link on placeholder page for electrical specifications/pinouts for WebLINX users 8/27/99 (1.7) Included missing IOB Propagation Delay page (6-113) 2/11/00 (1.8) Altered IOB heads (Acrobat PDF file problem), corrected Dual-port Write Mins for -4 speed grade. February 11, 2000 (Version 1.8) 6-117 6